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Recent system-level dynamic, that is, simulation-based performance estimation techniques have enabled faster assessment of the design alternatives, and thus the design space exploration DSE of complex embedded systems. In this context, the development of system environment models able to reflect common and feasible use cases is crucial for achieving efficient and valid solutions at early design stages. However, such environment modelling can be as or more complex and costly than the system model development itself.

The adoption of model-driven development MDD , component-based design CBD and abstraction, can improve the productivity of the environment specification as it does for system specification. In this chapter, a multi-level model-driven methodology for the specification of executable environments is presented.

The methodology supports the capture of the environment use cases by relying on the UML standard language and on standard profiles, i. Moreover, a SystemC executable counterpart is automatically generated from the UML-based environment model, coupling the documental and performance analysis levels. Thus, different abstraction levels are supported in the functional modeling of the environment.

This paper describes the concept for a distributed demand management program based on bi-directional communication involving an energy management system of a Grid Responsive Energy Efficient Networked GREEN home and the energy supplier in the Smart Grid. Our demand management approach uses in-home energy consumption monitoring and forecasting of future demands, which are in aggregated form available to the supplier as a day-ahead and intra-day forecasts. The supplier uses these forecasts to achieve higher precision of trading, and consequently reduce total energy cost.

This trading gain he can share with his customers participating in such a program. Performing accurate design simulations that entail exhaustive design space exploration has become infeasible with the increasing complexity of nano-CMOS circuits and systems integration, coupled with aggressive scaling of process technologies. With ever shrinking time to market pressures, the simulation time proves to be impractical as it can lead to longer design cycle times.

The simulation time factor is further aggravated by additional design and process parameters which have to be accounted for due to increased sensitivity in deeply scaled technologies.

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In order to mitigate this problem, this chapter presents a two-stage approach that uses layout-accurate metamodels and efficient search algorithms for fast mixed-signal circuit and system optimization. First, the metamodel creation process is presented. A simulated annealing based optimization algorithm is then discussed for power optimization of the PLL components.

Low power consumption or high execution speed is achieved by making an application specific design. Finding a good trade-off between reconfigurability and performance is a challenge. This work presents a design methodology to generate application-domain specific heterogeneous coarse-grain reconfigurable architectures.

The specification of the reconfigurable architecture is given by a set of example applications which define the whole range of its required functionality. These applications are analyzed to extract common building blocks, which can be reused between them. In the next step, the circuits of the application are merged to a single reconfigurable module. The major part of this work describes the according tool and its algorithm. Its main task is to optimize the interconnect by hierarchically grouping the functional units.

System-on-Chip Methodologies & Design Languages

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Let us wish you a happy birthday! Date of Birth. Day 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Month January February March April May June July August September October November December Year Ghenassia, S. Swan, J. Kunkel, Transaction based design: another buzzword or the solution to a design problem? Brandolese, L: Ceresoli, W.

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Fornaciari, D. Sciuto, Library functions timing characterization for source-level analysis, Proc. Salvemini, M. Sami, D.

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Sciuto, A. Sciuto, A model of soft error effects in generic IP processors, Proc. DFT , October pp. Cordone, F. Santambrogio, G.

Sciuto, Using speculative computation and parallelizing techniques to improve scheduling of control based designs, Proc. Beltrame, D. Silvano, D. Lyonnard, C. Design, Automation and Test in Europe, July 17—20, , pp. Amicucci, F.